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OCX160 Crosspoint Switch
Features
667 Mb/s port data bandwidth, >50Gb/s aggregate bandwidth Low power CMOS, 2.5V and 3.3V power supply SRAM-based, in-system programmable 160 configurable I/O ports - 80 dedicated differential input ports - 80 dedicated differential output ports - Supports LVDS and LVPECL I/O - LVTTL control interface - Output Enable control for all outputs * Non-blocking switch matrix - Patented ActiveArrayTM matrix for superior performance - Double-buffered configuration RAM cells for simultaneous global updates - ImpliedDisconnectTM function for single cycle disconnect/ connect * * * * * Full Broadcast and multicast capability - One-to-One and One-to-Many connections - Special broadcast mode routes one input to all outputs at maximum data rate * Registered and flow-through data modes - 333 MHz synchronous mode - 667 Mb/s asynchronous mode - Low jitter and signal skew - Low duty cycle distortion * RapidConfigureTM parallel interface for configuration and readback * JTAG serial interface for configuration and Boundary Scan testing * 420 BGA package with 1.27mm ball spacing
Preliminary Data Sheet
Description
The OCXTM family of SRAM-based devices are non-blocking n X n digital crosspoint switches capable of data rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports. The input ports support flow-through mode only. The output ports are individually programmable to operate in either flowthrough (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a global clock or a next neighbor clock source. The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a traditional n:1 multiplexer architecture. The OCX devices support various operating modes covering one input to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on all unchanged data paths. The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch matrix. Readback is supported for device test and verification purposes. The OCX160 also supports the industry standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to download configuration data to the device and readback data. A functional block diagram of the OCX160 is shown in Figure 1.
Applications
* SONET/SDH and DWDM * Digital Cross-Connects
160 IN[79:0] Input Buffers 80 x 80 Crosspoint Switch Matrix
* System Backplanes and Interconnects * High Speed Test Equipment
160 OUT[79:0] Output Buffers
* ATM Switch Cores * Video Switching
2 CLK OE#
RapidConfigure Signals
RCA[6:0] 7 RCB[6:0] 7 RCI[3:0] 4 RCO[4:0] 5 RC_CLK# RC_EN# UPDATE#
Configuration and Programming Logic
TCK TMS TDI TRST# TDO
JTAG Signals
HW_RST#
Figure 1 OCX160 Functional Block Diagram I-Cube, Inc. [Rev. 1.6] 2/20/01 1
OCX160 Crosspoint Switch--Preliminary Data Sheet
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Contents
1. 1.1 Introduction ........................................................................................................................... 7 Input and Output Buffers...................................................................................................... 8 Input and Output Port Function Mode ........................................................................... 8 Broadcast Mode ............................................................................................................. 9
1.1.1 1.1.2 1.2
Output Buffer Configuration ................................................................................................ 9 Output Control Signals................................................................................................... 9 Neighboring Output Port as a Clock Source .................................................................. 9
1.2.1 1.2.2 1.3
RapidConfigure Interface ....................................................................................................11 RapidConfigure Programming Instructions.................................................................. 11 ImpliedDisconnect ....................................................................................................... 13
1.3.1 1.3.2 1.4
JTAG Configuration Controller.......................................................................................... 14 JTAG Interface............................................................................................................. 14 Output Port Configuration ........................................................................................... 14 Switch Matrix Configuration ....................................................................................... 14 Mode Control Register Configuration.......................................................................... 14 JTAG Architecture and Shift Registers ........................................................................ 15 JTAG State Machine .................................................................................................... 16 JTAG Input Format ...................................................................................................... 16 JTAG Instructions ........................................................................................................ 17
1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.5 2. 3. 3.1 3.2 3.3 3.4 4. 4.1 4.2
Device Reset Options ......................................................................................................... 20 Pin Description .....................................................................................................................21 Differential I/O Standards ...................................................................................................22 LVDS ................................................................................................................................. 22 LVPECL ............................................................................................................................. 23 Termination Resistor Packs ................................................................................................ 24 Mixed I/O Systems............................................................................................................. 24 Electrical Specifications .......................................................................................................25 Absolute Maximum Ratings .............................................................................................. 25 Recommended Operating Conditions ................................................................................ 25
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OCX160 Crosspoint Switch--Preliminary Data Sheet
4.3 4.4 4.5 4.6 5. 5.1 5.2 5.3 5.4 5.5 6. 6.1 6.2 7. 8. 9. Pin Capacitance ................................................................................................................. 25 DC Electrical Specifications............................................................................................... 26 AC Electrical Specifications............................................................................................... 27 Timing Diagrams................................................................................................................ 28 Package and Pinout ............................................................................................................. 32 Package Pinout ................................................................................................................... 32 Pinout by Ball Sequence..................................................................................................... 33 Pinout by Ball Name .......................................................................................................... 36 Package Dimensions........................................................................................................... 38 Package Thermal Characteristics........................................................................................ 39 Power Consumption ............................................................................................................ 40 Power for LVDS I/O .......................................................................................................... 40 Power for LVPECL I/O ..................................................................................................... 41 Component Availability and Ordering Information ......................................................... 42 Glossary ................................................................................................................................ 42 Product Status Definition .................................................................................................... 44
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 OCX160 Functional Block Diagram .................................................................................................... 1 OCX160 Switch Matrix ........................................................................................................................ 7 Input and Output Buffer Configuration ................................................................................................ 8 Next Neighbor Clock Block Diagram ................................................................................................ 10 OCX160 JTAG Architecture .............................................................................................................. 15 OCX160 JTAG State Machine ........................................................................................................... 16 Transmitting LVDS Signal Circuit ..................................................................................................... 22 Receiving LVDS Signal Circuit ......................................................................................................... 22 Transmitting LVPECL Signal Circuit ................................................................................................ 23 Receiving LVPECL Signal Circuit..................................................................................................... 23 Registered Output Mode Timing ........................................................................................................ 28 Flow-Through Mode Timing .............................................................................................................. 28 Output Enable Timing ........................................................................................................................ 28 Duty Cycle Distortion ......................................................................................................................... 29 RapidConfigure Write Cycle .............................................................................................................. 29 RapidConfigure Read Cycle ............................................................................................................... 30 JTAG Timing ...................................................................................................................................... 30 Typical Performance LVDS mode ..................................................................................................... 31 Typical Performance LVPECL mode................................................................................................. 31 OCX160 Package Pinout .................................................................................................................... 32 OCX160 Package--Bottom, Top and Side Views ............................................................................. 38 Power Consumption Diagram for the OCX160 using LVDS............................................................. 40 Power Consumption Diagram for the OCX160 using LVPECL........................................................ 41
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Tables
Table 1
Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24
Summary for Programmable I/O Attributes for OCX160 ................................................................. 8
Next Neighbor Outputs.................................................................................................................... 10 RapidConfigure Programming Instructions .................................................................................... 11 RCO[4:0] Readback Pin Assignment.............................................................................................. 13 Programming an Output Buffer using RapidConfigure .................................................................. 13 Mode Control Register .................................................................................................................... 14 JTAG Input Format ......................................................................................................................... 16 JTAG Instructions ........................................................................................................................... 17 Programming an Output using JTAG.............................................................................................. 19 Number of JTAG Cycles and Configuration Time ......................................................................... 19 Device Reset Options ...................................................................................................................... 20 OCX160 Pin Description................................................................................................................. 21 Termination Resistor Packs............................................................................................................. 24 Supply Voltages and Terminating Resistors ................................................................................... 24 Absolute Maximum Ratings............................................................................................................ 25 Recommended Operating Conditions.............................................................................................. 25 Pin Capacitance ............................................................................................................................... 25 LVTTL DC Electrical Specifications.............................................................................................. 26 LVDS DC Electrical Specifications ................................................................................................ 26 LVPECL DC Electrical Specifications ........................................................................................... 26 AC Electrical Specifications............................................................................................................ 27 OCX160 Pinout By Ball Sequence.................................................................................................. 33 OCX160 Pinout By Ball Name ....................................................................................................... 36 Package Thermal Coefficients......................................................................................................... 39
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OCX160 Crosspoint Switch--Preliminary Data Sheet 1. Introduction
The OCX160 is a differential crosspoint-switching device. The main functional block of the device is a Switch Matrix as shown in Figure 1. The Switch Matrix is a x-y structure supporting an input-to-output data flow. Figure 2 shows a conceptual view of the switch matrix with inputs connected to the horizontal trace and outputs to the vertical trace. Connections between vertical and horizontal lines are implemented with a proprietary highperformance buffering circuit. Signal path delays through the Switch Matrix are very well balanced, resulting in predictable and uniform pin-to-pin delays. Note - For the purpose of clarity, the logic diagrams within this data sheet are conceptual representations only and do not show actual circuit implementation.
Data
Loading SRAM Cell
Active SRAM Cell
UPDATE#
Proprietary High-performance Buffering Circuit
Figure 2
OCX160 Switch Matrix
The Active SRAM cells are responsible for establishing connections in the switch matrix by turning on the interconnect circuit, while the Loading SRAM cell can be used to store a second configuration that can be transferred to the Active SRAM cell at a later time. The two SRAM cells are arranged so that a double buffered scheme can be employed. Through the use of an internal signal (generated automatically during a programming cycle) it is possible to store a second configuration map in the Loading SRAM while the Active SRAM maintains its present connection status. When the UPDATE# signal is asserted low, the contents of the Loading SRAM cell are transferred to the Active SRAM cell and the switch matrix connection is either made or broken. The UPDATE# signal can be used to control when the switch matrix is reconfigured. For instance, as long as the UPDATE# signal is asserted high, the Loading SRAM cells for the entire switch matrix could be changed without affecting the current configuration of the switch. When the UPDATE# signal is asserted low, the entire switch matrix would be reconfigured simultaneously. If the UPDATE# signal is asserted continuously, all crosspoint programming commands (generated by RapidConfigure or JTAG programming cycles) will take effect immediately, since the Loading SRAM cell's contents will be transferred directly to the Active SRAM cell.
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OCX160 Crosspoint Switch--Preliminary Data Sheet
1.1 Input and Output Buffers
All of the input buffers are differential inputs with flow-through mode. The output buffers are programmable for either flow-through or registered mode. Figure 3 shows the basic block diagram of the input and output blocks with the sources for the output control signals (OE# and CLK). The control signals are explained in more details in the following sections.
Output Mode Select Input Switch Matrix Output D Q
CLK Next Neighbor Clock Select
OE#
Figure 3
Input and Output Buffer Configuration
1.1.1 Input and Output Port Function Mode
The following legend describes the various modes of the Input and Output Ports and the specification used by the OCXProTM Software. Legend: Ax-Switch Matrix Signal Px-Port Signal OE#-Output Enable (# means "Active Low") CLK-Clock
Table 1 Symbol Px Ax Summary for Programmable I/O Attributes for OCX160 I/O Port Function Input - The external signal is buffered from the Input Port pin to the corresponding Switch Matrix line. Mnemonic IN
Ax
Px
Output - The internal signal is buffered from the corresponding Switch Matrix line to the Output Port pin. In this mode an optional output enable (OE#) can be selected. The default state is logic high with enable set to ON. Registered Output - The internal signal on the Switch Matrix line is registered by an edge-triggered register within the Output Port. A clock source is required in this mode. An output enable (OE#) is available but not required.
OP
OE# RO Ax CLK OE# Ax Px No Connect - In this mode, the output Port pin is isolated from the Switch Matrix. NC Px
D
Q
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OCX160 Crosspoint Switch--Preliminary Data Sheet
1.1.2 Broadcast Mode
The OCX160 has a special Broadcast Mode which connects any input to all outputs without performance degradation. The input is selected using RapidConfigure or JTAG and disconnects all other inputs. The Global Update pin (UPDATE#) must be held high during Broadcast Mode. Asserting the UPDATE# pin returns the array to the previous program condition.
1.2 Output Buffer Configuration
Every output port of the OCX160 can be configured as either a flow-through or registered output. In registered mode there are two clock sources that are available:
* *
Global Clock Next Neighbor
Additionally, there are output control signals.
1.2.1
Output Control Signals
Every output port of the OCX has a global Output Enable signal (OE#). All output buffers have output enables that have programmable polarity and are individually configurable. Additionally each output can be permanently enabled (always ON) or disabled (always OFF) which is useful for applications which need to tri-state outputs (for example when using multiple chips in expansion mode) or for power saving in designs that do not need to use all the outputs available. Two control bits are used to control the function of the output enable function as described in Table 5.
1.2.2
Neighboring Output Port as a Clock Source
A physically adjacent port can be used as a clock source for an output port configured in registered mode. These outputs are grouped in pairs such that the signal being switched through OUT0 can be used to clock the signal being switched through OUT1, and vice versa. Any single clock or data input signal can be used to clock any other input signal provided they are switched to an appropriate output pair (see Table 2). Figure 4 shows the implementation of next neighbor output port clocking in the OCX160 switch. For example, INx is used for data input while INy is used for the corresponding clock. INx is connected to OUT0 via the crosspoint array while INy is connected to OUT1 via the crosspoint array. OUT0 is configured in registered output (RO) mode with OUT1 as its next neighbor clock selection. OUT1 will output the clock signal as well as clock the data in OUT0. Adjacent port selection is required for next neighbor clocking in the registered output mode. This feature is useful in many applications where different types of data switching through the crosspoint array have various associated clocks. To match the delays in the data and corresponding clocks, it is common practice to pass the clocks through the switch along with the data.
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Crosspoint Array Any Input Port (INx) D CLK Next Neighbor Clock Select Q
Output Mode Select
OUT0
OE#
Output Mode Select Any Input Port (INy) D CLK Next Neighbor Clock Select OE# Q
OUT1
Figure 4
Next Neighbor Clock Block Diagram
The advantages of next neighbor clocking are: 1. Using next neighbor clocking in the registered output (RO) mode helps reduce the skew in outgoing data. 2. For a design with a large number of outputs switching simultaneously, next neighbor clocking mode is useful to stagger outputs for reduced board noise caused by simultaneous switching outputs. Note - Selecting the next neighbor clock for both outputs at the same time is not recommended. Only one output in the pair at a time can be clocked by its next neighbor.
Table 2 Next Neighbor Outputs
Pairing Sequence for Neighboring Outputs Output Next Neighbor Pairs 0,1 2,3 4,5 6,7 8,9 76,77 78,79
Only OUT1 can neighbor with OUT0, OUT3 with OUT2, etc. OUT2 cannot neighbor with OUT1, or OUT4 with OUT3, etc.
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OCX160 Crosspoint Switch--Preliminary Data Sheet
1.3 RapidConfigure Interface
RapidConfigure (RC) is a 25 signal parallel interface that is used to program the OCX160 device. The 25 pins are allocated as follows: RCA[6:0] = RapidConfigure Address A. RCA are input pins. RCB[6:0] = RapidConfigure Address B. RCB are input pins. RCI[3:0] = RapidConfigure Instruction Bits RCO[4:0] = RapidConfigure Readback. RCO are output pins. RC_CLK# = RapidConfigure Clock (negative edge clock) RC_EN# = RapidConfigure Cycle Enable (active low)
1.3.1
RapidConfigure Programming Instructions
The RC interface supports both write and read types of operations: 1. Write Operations (reset crosspoint and Input or Output Buffer (IOB), configure an Output Buffer, connect/disconnect crosspoint) 2. Read Operations (Output Buffer and crosspoint configuration read).
Table 3 RapidConfigure Programming Instructions RCO[4:0] Instruction Reserved Reserved X X Reset Crosspoint Array Set Array to Broadcast mode Reset the entire crosspoint array to no connect. All Output Buffers remain unchanged by this operation. Connects the input selected by RCB[6:0] to all output ports and disconnects all other inputs. The Global Update (UPDATE#) pin must be held high during Broadcast mode. Activating the Global Update pin returns the array to the previous program condition. Program an Output Buffer specified by RCA[6:0]. See Table 5 for RCB[6:0] bit assignment and buffer functionality. Description
RCI[3:0] 0000 0001 0010
RCA[6:0]
RCB[6:0]
0011
X
Input Port Address
0100
Output Port Address
Data
Configure an Output Buffer
0101 Cycle 1 Output Port Address Intput Port Address X
Readback Crosspoint, Output Buffer status
This is a two-cycle instruction. Specify the crosspoint connect status at input location specified by RCA[6:0] to the output location specified by RCB[6:0].
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Table 3 RCI[3:0] Cycle 2 RCA[6:0] X RapidConfigure Programming Instructions (Continued) RCO[4:0] Output Data Instruction Description Readback (using RCO[4:0]) the status of the input buffer specified in Cycle 1 by RCA[6:0], the output buffer specified in Cycle 1 by RCO[4:0] and the crosspoint connect status. See Table 4 for RCO[4:0] readback pin assignment. 0110 0111 X X X Input Port Address Input Port Address Update Disconnect Input Program the Global Update function without the use of the UPDATE# pin. Disconnect the crosspoint cells of the input row location specified by RCA[6:0]. Disconnect the crosspoint cell at the input location specified by RCA[6:0] to the output location specified by RCB[6:0]. All other connections from the source input address or to the same output address remain the same as before. 1001 Output Port Address Input Port Address Connect, with ImpliedDisconnect Connect the crosspoint cell at the input location specified by RCA[6:0] to the output location specified by RCB[6:0]. All other connections from the same input address or to the same output address are set to no connect (NC). 1010 Output Port Address Input Port Address Connect, without ImpliedDisconnect Connect the crosspoint cell at the input location specified by RCA[6:0] to the output location specified by RCB[6:0]. All other connections from the same input address remain the same as before. 1011 1100 1101 X X Reserved Reserved Reset All Reset the switch matrix to no connects (NC). Output Buffers default to flowthrough mode (OP) with output enable set to always enabled (ON). Output Buffer defaults to select Global Clock (CLK) source even though mode is OP.
RCB[6:0] X
1000
Output Port Address
Disconnect Input and Output
1110 1111
Reserved Reserved
Note - X = Don't care.
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Table 4 RCO[4:0] O4
RCO[4:0] Readback Pin Assignment Signal/Function Connection Status: 0 = No connection (NC) -- (default state at reset) 1 = Connected Clock Select: 0 = Global Clock -- (default state at reset) 1 = Next Neighbor Output Mode: 0 = Flow-through (OP) -- (default state at reset) 1 = Registered (RO) Output Enable: Output enabled (ON) - this is the default state at reset Output disabled (OFF) Output controlled by OE (active high) Output controlled by OE# (active low)
Readback Location Crosspoint
O3
Output Buffer
O2
Output Buffer
O1, O0 0,0 0,1 1,0 1,1
Output Buffer
Table 5
Programming an Output Buffer using RapidConfigure Signal/Function Don't care Clock Select: 0 = Global Clock 1 = Next Neighbor Output Mode: 0 = Flow-through (OP) 1 = Registered (RO) Output Enable: Output enabled (ON) - this is the default state at reset Output disabled (OFF) Output controlled by OE (active high) Output controlled by OE# (active low)
RCB[6:0] B6, B5, B4 B3
B2
B1, B0 0,0 0,1 1,0 1,1
1.3.2
ImpliedDisconnect
ImpliedDisconnect is a feature that provides the ability to make fast switch connection changes. When using the RC instruction "Connect, with ImpliedDisconnect" to establish a new connection, any existing connection to that output port is automatically broken. Thus, a connection change, i.e. breaking an existing connection and then making a new one, can be accomplished in one RapidConfigure cycle.
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OCX160 Crosspoint Switch--Preliminary Data Sheet
1.4 JTAG Configuration Controller
The Output port attributes and the Switch Matrix connections can be programmed using the JTAG serial bus. The RapidConfigure Interface can be enabled or disabled using the JTAG serial bus. The JTAG-based serial mode is always available for configuration regardless of whether the RapidConfigure mode is enabled or disabled. However, proper care must be taken when switching between JTAG and RapidConfigure for configuring the devices. Before attempting to change Switch Matrix connections or output port configuration through JTAG, the user must first ensure that the RapidConfigure mode is disabled by using JTAG serial mode to set the RCE bit to zero in the Mode Control Register.
1.4.1
JTAG Interface
The dedicated JTAG TAP interface is designed in compliance with the IEEE-1149.1. The standard interface has five pins: Test Data Out (TDO), Test Mode Select (TMS), Test Data In (TDI), Test Reset (TRST#), and Test Clock (TCK), which allow Boundary Scan Testing as well as device configuration and verification. The I-Cube supplied software will automatically generate the necessary bitstream from a higher-level textual description of the required configuration. Data on the TDI and TMS pins are clocked into the device on the rising edge of the TCK signal, while the valid data appears on the TDO pin after the falling edge of TCK. For more detailed information on JTAG programming, refer to the OCX160 Register Programming Manual.
1.4.2
Output Port Configuration
Output port configuration is accomplished by loading the appropriate bitstream into the programming registers present at each Output port. The JTAG serial bus is used to load configuration data into the Output port programming registers, one Output port at a time.
1.4.3
Switch Matrix Configuration
The contents of the SRAM cells controlling Switch Matrix connection can be modified using the JTAG. This is accomplished by loading the configuration data, one word at a time, into the SRAM cells in the Switch Matrix.
1.4.4
Mode Control Register Configuration
The OCX160 contains a single bit Mode Control Register used to store user flags for RapidConfigure Enable (RCE). These are required for proper functioning of the device. The contents of this register can be changed using the JTAG interface and a special JTAG instruction.
Table 6 RCE 0 1
Mode Control Register Mode RapidConfigure interface disabled (OFF) RapidConfigure interface enabled (ON)
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OCX160 Crosspoint Switch--Preliminary Data Sheet
1.4.5 JTAG Architecture and Shift Registers
Boundary Scan Register (189 x 2 = 378 Bits)
JTAG Data Register - 1 Bit
Device Identification Register - 32 Bits TDI Mode Control Register - 1 Bits
MUX
BUF
TDO
JTAG Address Register - 7 Bits
Bypass Register - 1 Bit
Instruction Register - 16 Bits
TMS TCK
Figure 5 OCX160 JTAG Architecture
TAP Controller
TRST#
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OCX160 Crosspoint Switch--Preliminary Data Sheet
1.4.6 JTAG State Machine
1
Test Logic Reset 0 1 Run Test/ 1 Idle Select DR Scan 0 Capture DR 0 1 1 Select IR Scan 0 Capture IR 0 1
0
0
Shift DR 1 Exit 1 DR 1 0 Pause DR 1
0
Shift IR 1 Exit 1 IR 1 0 Pause IR 1
0
0
0
Exit 2 DR 1 Update DR 1 0
0
Exit 2 IR 1 Update IR 1 0
Figure 6
OCX160 JTAG State Machine
1.4.7
JTAG Input Format
Table 7 Instruction Bit Number Bit Name 15 I3 14 I2 13 I1 12 I0 11 10 BB BA JTAG Input Format Data 9 B9 8 B8 7 B7 6 A6 5 A5 Address A 4 A4 3 A3 2 A2 1 A1 0 A0
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OCX160 Crosspoint Switch--Preliminary Data Sheet
1.4.8 JTAG Instructions
Table 8 I [3:0] 0000 0001 0010 BB X X X BA X X X B9 X X X B8 X X X B7 X X X JTAG Instructions A6-A0 X X X Instruction Sample/EXTEST Sample/EXTEST Description Places the device in scan mode. Places the device in scan mode.
Reset the Crosspoint Resets the entire Crosspoint Array to no-connect. All Array other Output Buffer configurations are unchanged by this operation. Set Array for Broadcast mode Use the JTAG Address Register as the Input address to be the broadcast input Connects the selected Input to all Output cells and disconnects all other Inputs. Activating the Global Update JTAG instruction returns the Crosspoint array from the Broadcast mode to the previous programed state. Programs the Output Buffer address specified in the JTAG instruction (A6-A0). The configuration data is also specified in the JTAG instruction bits BA-B7. See Table 9 for bit assignment of the Buffer functionality. Readback the connectivity of the Crosspoint cell with the Input location specified in the JTAG Address Register and the Output location specified JTAG instruction (A0-A6). It also returns the configuration of the Output Buffer addressed in the JTAG instruction (A0-A6). The readback data is shifted out of TDO in the following sequence: 1. Crosspoint Connect (1=connected, 0=no connection) 2. Output Enable--B7 (see Table 9) 3. Output Enable--B8 (see Table 9) 4. Output Data Source--B9 (0=Flow-through, 1=registered) 5. Output Clock Select--BA (0=Global Clock, 1=Next Neighbor) 6. State of Broadcast bit 7. State of the RCE bit NOTE: This instruction does not increment the JTAG Address Register. This instruction also requires two DR cycles
0011
X
X
X
X
X
X
0100
X
Clock Data Select Mode
OE
OE
Output Buffer Address
Program a Buffer
0101
X
X
X
X
X
Output Address/ Configuration Buffer readback
0110 0111
X X
X X
X X
X X
X X
X X
Update the Crosspoint Array Disconnect Input cell
Update the programmed connection from the Loading SRAM to the Active SRAM. Disconnect the Crosspoint connections from the Input address specified in the JTAG Address Register.
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Table 8 I [3:0] 1000 BB X BA X B9 X B8 X B7 X JTAG Instructions (Continued) A6-A0 Instruction Description Disconnect the Crosspoint cell at the Input location specified at the JTAG Address Register and the Output location specified in the Disconnect JTAG instruction (A6-A0). All other connections from the same input address or to the same output address remain the same. Connects the Crosspoint cell at the Input location specified on the JTAG Address Register and the output location specified in the Connect JTAG instruction (A6-A0). All other connections from the same Input address or the same Output address are set to no-connects. NOTE: This instruction increments the JTAG Address Register (Input address). Connects the Crosspoint cell at the Input address specified in the JTAG Address Register and the Output address specified in the Connect JTAG instruction (A6-A0). All other connections from the same input remain the same as before. Sets the 7-bit JTAG Address Register with the 7-bit address (A6-A0) of the JTAG Instruction Register. The 7-bit address of the JTAG Address Register becomes the Input port address for Crosspoint Access. Serialize the device ID and revision history out to TDO. ID for the OCX160 is 0x0000B89F
Output Address Disconnect Input and Output
1001
X
X
X
X
X
Output Address Connect with ImpliedDisconnect
1010
X
X
X
X
X
Output Address Connect--no ImpliedDisconnect
1011
X
X
X
X
X
Input Address
Set the JTAG Address Register
1100 1101
X X
X X
X X
X X
X X
X X
Device ID out
Reset Output Buffer Resets the Crosspoint Array to no-connects. Sets the and Crosspoint Output buffer to Flow-through mode with Output Array Enabled. The device ID is serialized to TDO. Set RCE Bit Sets the RCE bit of the Mode Control Register with the JTAG instruction bit A0. To turn ON the RCE bit, encode bit A0 to 1. To turn OFF the RCE bit, encode bit A0 to 0. Places device in a mode to pass TDI data to TDO with one clock delay. Used for programming and testing devices through serial connected JTAG controls.
1110
X
X
X
X
X
X
1111
X
X
X
X
X
X
Bypass
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Table 9 BA, B9, B8, B7 BA
Programming an Output using JTAG Signal/Function Clock Select: 0 = Global Clock 1 = Next Neighbor Output Mode: 0 = Flow-through (OP) 1 = Registered (RO) Output Enable: Output enabled (ON) - this is the default state at reset Output disabled (OFF) Output controlled by OE (active high) Output controlled by OE# (active low)
B9
B8, B7 0,0 0,1 1,0 1,1
Table 10
Number of JTAG Cycles and Configuration Time OCX160 Operation JTAG Cycles 7 28 28 2,240 35 56 181,440 183,680
JTAG Reset Sequence (TMS = "11111") Enable or Disable RapidConfigure Change attributes of ONE Output Port Change attributes of ALL Output Ports Reset JTAG Controller + Reset ALL Output Ports + Clear ALL SRAM cells Connect or disconnect two Ports Configure Entire Switch Matrix Completely Configure the Device (All Output Ports and All Switch Matrix Connections)
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OCX160 Crosspoint Switch--Preliminary Data Sheet
1.5 Device Reset Options
The power-on reset, RapidConfigure reset, hardware reset, and JTAG reset functions will program the output buffers to flow-through mode (with Global Clock selected), and Output Enabled (ON). JTAG can be reset via the TRST# pin or by clocking five consecutive one to the TMS pin. The hardware reset pin can be done accomplished through the HW_RST# pin (active low). RC reset can be accomplished by applying the RC instruction 1101 to the RCI[3:0] pins.
Table 11 Programming Interface Reset Method Power-on Reset Hardware Reset HW_RST# (low pulse) 1. Low Pulse on TRST# 2. TMS high for 5 TCLK cycles JTAG Reset 3. Device Reset (instruction 1101) 4. Reset Crosspoint Array (instruction 0010) RapidConfigure Reset 1. Device reset (instruction 1101) 2. Reset Crosspoint Array (instruction 0010) Device Reset Options Output Ports OP OP Unchanged Unchanged OP Unchanged OP Unchanged Switch Matrix NC NC Unchanged Unchanged NC NC NC NC RCE Mode Control 1 (RC Enabled) 1 (RC Enabled) Unchanged Unchanged 1 (RC Enabled) Unchanged 1 (RC Enabled) Unchanged JTAG TAP TLR1 TLR TLR TLR TLR Unchanged Unchanged Unchanged
1. TLR = Test Logic Reset state.
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OCX160 Crosspoint Switch--Preliminary Data Sheet 2. Pin Description
Table 12 Pin Name INP[79:0] INN[79:0] OUTP[79:0] OUTN[79:0] CLKP CLKN OE# HW_RST# UPDATE# # of Pins 80 80 80 80 1 1 1 1 1 OCX160 Pin Description Description Non-inverting differential input signals Inverting differential input signals Non-inverting differential input signals Inverting differential input signals Non-inverting differential Global Clock Inverting differential Global Clock Global Output Enable Hardware Reset Global Update
Type Input Input Output Output Input Input Input Input Input
RC Pins
RCA[6:0] RCB[6:0] RCO[4:0] RCI[3:0] RC_CLK# RC_EN# 7 7 5 4 1 1 Input Input Output Input Input Input RapidConfigure Address A RapidConfigure Address B RapidConfigure Readback RapidConfigure Instruction Bits RapidConfigure Clock RapidConfigure Cycle Enable
JTAG Pins
TCK TMS TDI TRST# TDO 1 1 1 1 1 Input Input Input Input Output JTAG Test Clock JTAG Test Mode Select JTAG Test Data In JTAG Test Reset JTAG Test Data Out
Power and Ground Pins
VDD.CORE VDD.PAD VDD.IN VSS
(2, 3) (1, 4)
12 8 8 36
2.5V Power 3.3V Power Ground
Core Voltage LVTTL Control pins Voltage and Differential Input Buffer Voltage Ground
2.5V or 3.3V Power Differential Output Buffer Voltage
NOTES: 1. Dedicated differential input buffers can receive both LVDS and LVPECL voltage levels using 3.3V supply. 2. VDD.PAD is 2.5V for LVDS outputs or 3.3V for LVPECL outputs. 3. Dedicated differential output buffers can be biased using different supplies for VDD.PAD and external resistors to support both LVDS and LVPECL output voltage levels. 4. The LVTTL control, JTAG pins, and differential input ports are 3.3V--they are not 5V tolerant. 5. The differential output pins powered from 2.5V are 3.3V tolerant.
I-Cube, Inc.
[Rev. 1.6] 2/20/01
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OCX160 Crosspoint Switch--Preliminary Data Sheet 3. Differential I/O Standards
The OCX160 support the two most popular differential signaling standards: Low Voltage Differential Signaling (LVDS) and Low Voltage Positive Emitter Coupled Logic (LVPECL). LVDS is typically used in communication systems as high speed, low noise point-to-point links. The OCX160 conforms to the ANSI/TIA/EIA-644 standard covering electrical specifications for output drivers and receiver inputs. LVPECL is commonly used in video switching applications or those designs requiring transmission of highspeed clock signals.
3.1 LVDS
LVDS is a differential signaling standard. It requires that one data bit is carried through two signal lines. As with all differential signaling standards, LVDS has an inherent noise immunity over single-ended standards. The voltage swing between two signal lines is approximately 350mV. The use of a reference voltage or a board termination voltage is not required. LVDS requires the use of two pins per input or output. LVDS requires external resistor termination. Transmitting and receiving circuits for LVDS are shown in Figures 7 and 8. OCX Device
Z0=50 to LVDS Receiver 165 RDIV 140 RS VDD.PAD=2.5V LVDS Output OUTN 165 Z0=50 to LVDS Receiver
OUTP 2.5V
RS
Data Transmit
Figure 7
Transmitting LVDS Signal Circuit
Z0=50
INP
OCX Device
+ -
from LVDS Driver Z0=50
RT 100
Data Recieve
INN
Figure 8
Receiving LVDS Signal Circuit
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OCX160 Crosspoint Switch--Preliminary Data Sheet
3.2 LVPECL
LVPECL is another differential signaling standard that specifies two pins per input or output. The voltage swing between these two signal lines is approximately 850 mV. The use of a reference voltage or a board termination voltage is not required. The LVPECL standard requires external resistor termination. Transmitting and receiving circuits for LVPECL are shown in Figures 9 and 10.
OCX Device
OUTP 3.3V
RS 100 RDIV 187 RS
Z0=50 to LVPECL Receiver
Data Transmit
Z0=50 to LVPECL Receiver
VDD.PAD=3.3V LVPECL Output
OUTN 100
Figure 9
Transmitting LVPECL Signal Circuit
Z0=50
INP
OCX Device
+ -
from LVPECL Driver
RT 100 Z0=50 INN
Data Recieve
Figure 10 Receiving LVPECL Signal Circuit
I-Cube, Inc.
[Rev. 1.6] 2/20/01
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OCX160 Crosspoint Switch--Preliminary Data Sheet
3.3 Termination Resistor Packs
Resistor packs are available with the values and the configuration required for LVDS and LVPECL termination from Bourns, Inc. The part numbers are listed in Table 13. For pricing and availability questions, please contact them directly at www.bourns.com.
Table 13 Bournes Part Number CAT16-LV2F6 CAT16-LV4F12 CAT16-PC2F6 CAT16-PC4F12 CAT16-PT2F2 CAT16-PT4F4 Termination Resistor Packs Termination for: Driver Driver Driver Driver Receiver Receiver Pairs per Pack 2 4 2 4 2 4 No. of Pins 8 16 8 16 8 16
Differential I/O Standard LVDS LVDS LVPECL LVPECL LVDS/LVPECL LVDS/LVPECL
3.4 Mixed I/O Systems
The use of different supply voltages and terminating resistors allows the OCX160 to support LVDS / LVPECL translation as well as switching as outlined in Table 14.
Table 14 Input LVDS LVPECL LVDS LVPECL Supply Voltages and Terminating Resistors Output LVDS LVDS LVPECL LVPECL VDD.PAD 2.5V 2.5V 3.3V 3.3V RT 100 100 100 100 RS 165 165 100 100 RDIV 140 140 187 187
NOTES: 1. VDD.IN = 3.3V 10%, VDD.CORE = 2.5V 5% 2. It is not possible to mix LVDS and LVPECL outputs on a device
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[Rev. 1.6] 2/20/01
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OCX160 Crosspoint Switch--Preliminary Data Sheet 4. Electrical Specifications
4.1 Absolute Maximum Ratings
Table 15 Symbol VDD.CORE VDD.IN VDD.PAD VIN TJ TSTG PMAX ESD
6
2
Absolute Maximum Ratings1 Parameter Limits -0.3 to +3.0 -0.3 to +3.6 -0.3 to +3.6 -0.3 to +3.63 +150 -65 to +150 6 2000 Units V V V V C C W V
Supply Voltage (core) Supply Voltage (inputs) Supply Voltage (differential outputs) Input Voltage Junction Temperature Storage Temperature Maximum Power Dissipation Electrostatic Discharge
4.2 Recommended Operating Conditions
Table 16 Symbol VDD.CORE VDD .PAD4 VDD.IN TA Recommended Operating Conditions Parameter Supply Voltage (core) Supply Voltage (differential output buffers) Supply Voltage (inputs) Operating Temperature: Commercial Operating Temperature: Industrial Limits +2.375 to +2.625 3.3V 10% to 2.5V 5% +3.0 to +3.6 0 to +70 -40 to +85 Units V V V C
4.3 Pin Capacitance
Table 17 Symbol CPIN
1. 2. 3. 4. 5. 6.
Pin Capacitance5 Parameter Max 10 Units pF
Signal Pin Capacitance
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. A maximum undershoot of 2V for a maximum duration of 20 ns is acceptable. Overshoot to 3.6V is acceptable. All inputs are 3.3V tolerant with the VDD pin at 2.5V or 3.3V. Note that min and max values for VDD for differential outputs are I/O Standard dependent. Capacitance measured at 25C. Sample tested only. Measured using Human Body Model.
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[Rev. 1.6] 2/20/01
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OCX160 Crosspoint Switch--Preliminary Data Sheet
4.4 DC Electrical Specifications
(TA = -40C to 85C, VDD.IN = 3.3V 10%, VDD.CORE = 2.5V 5%) Table 18 Symbol VIH VIL VOH VOL ILIH, ILIL (1) ILOZ Parameter High-level Input Low-level Input High-level Output Low-level Output Input Pin Leakage Current Tristate Leakage Output OFF State LVTTL DC Electrical Specifications Conditions Ports are 3.3V tolerant Ports are 3.3V tolerant VDD.PAD = Min IOH = -4mA VDD.PAD = Min IOL = 8mA VDD.IN= Max 0.0 < In < VDD.PAD VDD.PAD = Max 0.0 < In < VDD.PAD Min 2.0 -0.3 2.4 Max 3.6 0.8 VDD.PAD+ 0.3 0.4 +5 -50 +5 -5 Units V V V V
Power
PDDQ
(2)
Quiescent Power
All VDD = Max
0.5
W
Table 19
LVDS DC Electrical Specifications Min
(3)
DC Parameter Output High Voltage for OUTP and OUTN Output Low Voltage for OUTP and OUTN Differential Output Voltage Differential Input Voltage Input Common-Mode Voltage
1. 2. 3. 4. 5. All LVTTL input pins have pull-up resistors. See section 6 for dynamic power consumption calcualtion. Refer to Figures 7 and 8 for termination resistor. Refer to Figures 9 and 10 for termination resistor. Maximum capacitive load is 12 pF.
(5)
Typ
Max 1.6
Units V V mV V mV V
0.90 250 100 0.25 350 350 1.25 2.25 450 1.125 1.25 1.375
Output Common-Mode Voltage
Table 20
LVPECL DC Electrical Specifications Min VDD.PAD - 1.165 VDD.PAD - 1.810 1.80 0.95 Max VDD.PAD - 0.880 VDD.PAD - 1.475 2.40 1.55
DC Parameters VIH (4) VIL VOH VOL
These values in Table 20 are valid at the output of the source termination pack, as shown in sections 3.2 and 3.3, with a 100 differential load only. The VOH levels are 200mV below LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. The above table summarizes the DC output specifications of LVPECL.
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OCX160 Crosspoint Switch--Preliminary Data Sheet
4.5 AC Electrical Specifications
(VDD.IN = 3.3V 10%, VDD.CORE = 2.5V 5%) Table 21 AC Electrical Specifications 0C to 70C Symbol RDATA FRO tW_RO tS_RO tH_RO tCO_RO tPHL, tPLH tW+ tWtDCD+, tDCDtJITTER tSK tPHZ_OT, tPLZ_OT tPZH_OT, tPZL_OT tRC tW+_RC tW-_RC tS_RC tH_RC tP_UD fJTAG tW_JTAG tS_JTAG tH_JTAG tP_JTAG NOTES:
1. These parameters are guaranteed but not tested in production.
-40C to +85C Min Max 667 333 2 4 0 Units Mb/s MHz ns ns ns 2.5 6.5 1.5 1.5 ns ns ns ns 0.6 TBD TBD 0.6 3 3 12 5 4 4 ns ps ns ns ns ns ns ns ns 10 20 20 4 0 30 ns MHz ns ns ns 20 ns
Parameter NRZ Data Rate
(1) (1) (1)
Min
Max 667 333
Registered Output Clock Frequency
Registered Clock Pulse Width, High or Low Registered Output Setup Time to Clock Registered Output Clock to Hold Data Registered Output Clock to Data Out Valid
2 4 0 2.5 5.5 1.5 1.5 0.5 TBD TBD 0.5 3 3 12 5 3 3 10 20 20 4 0 20 30
One Way Signal Propagation Delay, Fanout = 1 Input Flow-through Positive Pulse Width Input Flow-through Negative Pulse Width Duty Cycle Distortion Output Jitter Skew between Output Ports Output Enable to Valid Data Output Enable to High Z State RapidConfigure Clock Period RapidConfigure Clock Pulse Width RapidConfigure Address Setup to RC_CLK# RapidConfigure Address and Enable Hold Time to RC_CLK# Update of Crosspoint to Data Out JTAG Clock Frequency (TCK) JTAG Clock Pulse Width (TCK) @ 20MHz cycle JTAG Setup Time JTAG Hold Time JTAG Clock to Output Data Valid (TDO)
(1)
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[Rev. 1.6] 2/20/01
27
OCX160 Crosspoint Switch--Preliminary Data Sheet
4.6 Timing Diagrams
Note - For the purpose of clarity, the timing diagrams within this data sheet are conceptual representations only and do not show actual circuit implementation.
tW_RO CLK tS_RO tH_RO IN
InPort CLK
tW_RO
RO
Switch Matrix
D Q OutPort
InPort OutPort
Dn Dn-1 tCO_RO
Dn+1 Dn Dn+1
Figure 11 Registered Output Mode Timing
InPort 1 InPort 2
tW+ tPLH tPHL
IN
InPort 1
OP
OutPort 1
OutPort 1 tSK
OutPort 2
Switch Matrix
InPort 2
tSK
OutPort 2
Figure 12 Flow-Through Mode Timing
OE#
InPort IN
InPort OE#
tPZH_OT tPZL_OT tPLZ_OT
tPHZ_OT
Switch Matrix
OP
OutPort
OutPort
Figure 13 Output Enable Timing
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OCX160 Crosspoint Switch--Preliminary Data Sheet
IN InPort
Switch Matrix
OP OutPort
InPort
tIN+
tIN-
OutPort
tOUT+ tDCD+ = tIN+ - tOUT+ tDCD- = tIN- - tOUT-
tOUT-
Figure 14 Duty Cycle Distortion
tRC tW+_RC RC_CLK# tS_RC RCA/RCB Address, Instruction tS_RC tH_RC RC_EN# tH_RC tW-_RC
tRC
Figure 15 RapidConfigure Write Cycle
I-Cube, Inc.
[Rev. 1.6] 2/20/01
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OCX160 Crosspoint Switch--Preliminary Data Sheet
tRC tW+_RC RC_CLK# tW-_RC
tRC
tS_RC RCA/RCB Address, Instruction
tH_RC
tS_RC tH_RC RC_EN#
Data Valid
RCO
High Impedance
Figure 16 RapidConfigure Read Cycle
tW_JTAG TCK
tW_JTAG
tS_JTAG tH_JTAG TDI, TMS tP_JTAG TDO
Figure 17 JTAG Timing
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[Rev. 1.6] 2/20/01
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Typical Performance at 667 Mb/s with PRBS Data (Currently not available for this document)
Figure 18 Typical Performance LVDS mode
Typical Performance at 667 Mb/s with PRBS Data (Currently not available for this document)
Figure 19 Typical Performance LVPECL mode
I-Cube, Inc.
[Rev. 1.6] 2/20/01
31
OCX160 Crosspoint Switch--Preliminary Data Sheet 5. Package and Pinout
5.1 Package Pinout
12 A B C D E F G H J K L M N P R T U V W
OUT51N VSS
34567
IN40N IN42N IN41N IN40P IN41P VSS RCI2 RC_EN# RCI1 VSS RCB4 VSS RCB5 OUT77P RCB6 OUT77N VDD.PAD OUT76P OUT71P OUT71N VDD.CORE RCI0 IN43N VDD.IN RCI3 IN43P IN45P IN42P IN44P IN45N IN44N IN48P IN48N
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
IN51N IN49N IN51P IN49P IN47N IN47P IN52P IN46N IN52N VDD.CORE IN50N IN54N IN55N IN54P VDD.IN VSS VSS IN50P IN53N IN55P IN60P VSS IN62N VDD.IN IN56N IN53P IN57P IN60N IN61P IN62P IN63N VSS IN56P IN57N IN58N IN64P IN61N IN63P IN68N IN69N VDD.IN VDD.CORE IN72N IN58P IN64N IN59N IN65P IN68P IN69P IN71N IN72P NC VSS IN59P IN65N IN66N IN67P IN71P IN74P IN75N TCK TRST# IN66P IN67N IN70N IN73P IN75P IN79N VSS TDO OUT07N IN70P IN73N IN74N IN79P TDI VSS OUT01P OUT01N IN78P IN78N IN76N IN77N IN76P IN77P VSS HW_RST# OUT00P OUT00N RCO4 VSS
VSS RC_CLK#
OUT78P
VSS
OUT78N OUT79P OUT79N OUT75P OUT75N OUT74N OUT74P OUT73N OUT73P OUT72N OUT72P OUT67N OUT67P OUT66N OUT66P OUT65N OUT65P OUT64P OUT63N OUT61P OUT64N OUT61N OUT59P OUT55P OUT55N OUT57P OUT58N OUT57N OUT52P OUT46N OUT46P OUT56N OUT56P OUT44N OUT44P OUT51P OUT50N OUT48P OUT42N OUT42P OUT48N OUT40P RCB0 RCB1 RCA6 VSS VSS RCA5 IN36P IN36N VSS OUT40N OUT50P OUT45N OUT47N OUT52N OUT58P OUT53P OUT54N OUT59N OUT62N OUT63P OUT69N OUT69P OUT70P OUT76N
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
IN46P
VDD.CORE
40-79 Inputs
OUT07P UPDATE# OUT09N OUT02P OUT03N OUT03P OUT11N OUT05P OUT04P OUT16N OUT11P OUT09P
TMS
OUT02N
OUT16P OUT05N VDD.PAD OUT17N OUT04N
OUT70N OUT68N OUT68P VDD.PAD OUT62P OUT60P OUT60N VSS VSS VSS OUT54P VDD.PAD OUT53N OUT49N OUT49P VDD.CORE OUT47P VDD.CORE OUT45P VDD.PAD OUT43P OUT41P OUT43N RCB3 OUT41N VSS RCB2 RCA3 VSS IN39P RCA4 IN39N IN34N IN38N IN34P IN38P IN37N IN33P IN37P IN33N IN35P IN31P RCA2 IN31N IN35N
OCX160 in 420 BGA package
40-79 Outputs
OUT17P OUT06N VDD.CORE OUT18P OUT06P OUT18N OUT10P VDD.CORE OUT13P OUT08P OUT08N OUT12P OUT10N OUT15P OUT13N
Top View
0-39 Outputs
OUT15N OUT12N VDD.PAD OUT19P OUT14P VSS VSS VSS OUT20N OUT20P OUT22P OUT22N OUT25P OUT19N OUT28P OUT24P OUT14N OUT21N OUT24N OUT21P
OUT28N OUT25N VDD.PAD OUT23P OUT26P OUT23N OUT29N OUT29P OUT27P OUT26N
OUT30P OUT27N VDD.CORE OUT31N OUT32P OUT31P OUT37N OUT32N OUT34N OUT30N
Y AA AB AC AD AE AF
0-39 Inputs
VDD.CORE VDD.IN VSS IN29N IN28N IN29P IN30P IN27N IN32P IN27P IN32N IN26P IN26N IN25N IN24P IN28P IN25P IN22N IN24N IN19N IN23N IN22P IN20N IN19P IN18N IN17N IN23P IN21P IN20P IN15P IN18P IN17P IN16P IN11N VDD.IN IN21N VSS IN15N IN14N IN13N IN16N IN11P IN09N IN07N VSS VSS IN14P IN12N IN13P IN10N IN09P IN07P IN04N VDD.IN IN12P IN08N VDD.CORE IN05P VDD.IN IN03N IN05N IN10P IN06P IN04P IN03P RCO0 VDD.CORE IN06N IN08P IN30N
OUT37P OUT34P VDD.PAD OUT39P OUT35N OUT39N OUT38N VSS VSS OE# RCA1 RCA0 IN01N IN02P IN01P IN02N IN00N VSS VSS IN00P CLKN VSS CLKP VSS RCO3 RCO2 OUT38P RCO1 OUT33P OUT36N OUT36P OUT33N OUT35P
12
34567
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 20 OCX160 Package Pinout
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OCX160 Crosspoint Switch--Preliminary Data Sheet
5.2 Pinout by Ball Sequence
Table 22 Ball # Ball Name
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 VSS VSS IN40N IN41N IN42N IN44N IN48N IN49N IN51N IN56N IN56P IN57N IN58P IN64N IN59P IN65N IN66P IN67N IN70P IN73N IN78P IN78N IN76P IN77P RCO4 VSS
OCX160 Pinout By Ball Sequence Ball # Ball Name
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 OUT78P OUT78N VSS RCI2 RCI3 IN43P IN45N IN47P IN47N IN50N IN53N IN55P IN60N IN61P IN61N IN63P IN68P IN69P IN71P IN74P IN75P IN79N TDI VSS OUT00P OUT00N
Ball # Ball Name
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 RC_CLK# VSS IN40P IN41P IN42P IN44P IN48P IN49P IN51P IN50P IN53P IN57P IN58N IN64P IN59N IN65P IN66N IN67P IN70N IN73P IN74N IN79P IN76N IN77N VSS HW_RST#
Ball # Ball Name
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 OUT79P OUT79N RC_EN# VSS RCI1 IN43N IN45P IN46N IN52P IN52N IN54N IN55N IN60P VSS IN62P IN63N IN68N IN69N IN71N IN72P IN75N TCK VSS TDO OUT01P OUT01N
Ball # Ball Name
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 OUT75P OUT75N RCB4 RCB5 VSS RCI0 VDD.IN IN46P VDD.CORE VDD.CORE IN54P VDD.IN VSS VSS IN62N VDD.IN VSS VDD.CORE VDD.IN IN72N NC VSS TRST# UPDATE# OUT07N OUT07P
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Table 22 Ball # Ball Name
F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 L1 L2 L3 L4 L5 L22 L23 L24 L25 L26 T1 T2 T3 T4 T5 T22 T23 T24 T25 T26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 OUT74N OUT74P OUT77P OUT77N RCB6 TMS OUT02P OUT03N OUT09N OUT09P OUT65N OUT65P OUT63P OUT62P VDD.PAD OUT08N OUT08P OUT10N OUT13P OUT13N OUT57P OUT58N OUT58P OUT49P OUT49N VDD.PAD OUT22P OUT28N OUT25P OUT25N OUT51P OUT50N OUT50P OUT41N RCB3 OUT39N OUT39P OUT36N OUT35N OUT35P
OCX160 Pinout By Ball Sequence (Continued) Ball # Ball Name
H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 N1 N2 N3 N4 N5 N22 N23 N24 N25 N26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 OUT72N OUT72P OUT70P OUT71N OUT71P VDD.PAD OUT04P OUT05N OUT16N OUT16P OUT61P OUT64N OUT59N VSS VSS VSS OUT14P OUT14N OUT19P OUT21P OUT46N OUT46P OUT47N OUT45P VDD.CORE VDD.CORE OUT29N OUT27N OUT27P OUT30P
Ball # Ball Name
G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 M1 M2 M3 M4 M5 M22 M23 M24 M25 M26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 OUT73N OUT73P OUT76N OUT76P VDD.PAD OUT02N OUT03P OUT05P OUT11N OUT11P OUT64P OUT63N OUT62N OUT60N OUT60P VDD.PAD OUT12P OUT12N OUT15P OUT15N OUT57N OUT52P OUT52N OUT47P VDD.CORE OUT23N OUT23P OUT29P OUT26P OUT26N
Ball # Ball Name
J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 P1 P2 P3 P4 P5 P22 P23 P24 P25 P26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 OUT67N OUT67P OUT69P OUT70N VDD.CORE VDD.CORE OUT04N OUT06N OUT17N OUT17P OUT61N OUT59P OUT54N OUT54P VSS VSS VSS OUT19N OUT21N OUT24N OUT56N OUT56P OUT45N OUT43P VDD.PAD OUT31P OUT31N OUT32N OUT32P OUT30N
Ball # Ball Name
K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 R1 R2 R3 R4 R5 R22 R23 R24 R25 R26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 OUT66N OUT66P OUT69N OUT68P OUT68N VDD.CORE OUT06P OUT10P OUT18P OUT18N OUT55P OUT55N OUT53P OUT53N VDD.PAD OUT20P OUT20N OUT22N OUT28P OUT24P OUT51N OUT44P OUT44N OUT43N OUT41P VDD.PAD OUT37N OUT37P OUT34N OUT34P
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Table 22 Ball # Ball Name
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 OUT48P OUT42P OUT42N RCB2 VSS RCA2 IN35N VDD.IN VDD.CORE VSS VDD.IN IN21N VSS VSS VDD.IN IN12P VDD.CORE VDD.CORE IN05P VDD.IN RCO0 VSS OUT38N OUT38P OUT36P OUT33N
OCX160 Pinout By Ball Sequence (Continued) Ball # Ball Name
AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 RCB0 RCB1 VSS RCA4 IN39P IN37P IN31P IN30P IN29P IN28P IN23N IN22P IN20P IN15P IN14N IN13N IN13P IN10N IN10P IN06P IN03P RCA0 RCA1 VSS RCO3 RCO2
Ball # Ball Name
AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 OUT48N OUT40P OUT40N VSS RCA3 IN35P IN31N IN30N IN29N IN28N IN23P IN21P VSS IN15N IN14P IN12N IN08N IN08P IN06N IN05N IN03N OE# VSS VSS RCO1 OUT33P
Ball # Ball Name
AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 RCA6 VSS IN36N IN34N IN39N IN37N IN33N IN32P IN27N IN26N IN25P IN22N IN20N IN19P IN18P IN17P IN16N IN11P IN09P IN07P IN04P IN02P IN01N IN00P VSS CLKP
Ball # Ball Name
AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 VSS RCA5 IN36P IN34P IN38N IN38P IN33P IN32N IN27P IN26P IN25N IN24P IN24N IN19N IN18N IN17N IN16P IN11N IN09N IN07N IN04N IN02N IN01P IN00N CLKN VSS
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35
OCX160 Crosspoint Switch--Preliminary Data Sheet
5.3 Pinout by Ball Name
Table 23 Ball Name
CLKN CLKP OE# HW_RST# IN00N IN00P IN01N IN01P IN02N IN02P IN03N IN03P IN04N IN04P IN05N IN05P IN06N IN06P IN07N IN07P IN08N IN08P IN09N IN09P IN10N IN10P IN11N IN11P IN12N IN12P IN13N IN13P IN14N IN14P IN15N IN15P IN16N IN16P IN17N IN17P IN18N IN18P IN19N IN19P
OCX160 Pinout By Ball Name Ball # Ball Name
A5 B5 D6 C6 A6 B6 C7 D7 D8 E8 C9 C8 A7 B7 A8 B8 C10 B10 A9 B9 D10 D9 C11 B11 D11 E11 D12 C12 A10 A11 A12 B12 B13 A13 B15 A15 C13 D13 C15 C14 E15 D15 D16 C16 IN64N IN64P IN65N IN65P IN66N IN66P IN67N IN67P IN68N IN68P IN69N IN69P IN70N IN70P IN71N IN71P IN72N IN72P IN73N IN73P IN74N IN74P IN75N IN75P IN76N IN76P IN77N IN77P IN78N IN78P IN79N IN79P NC OUT00N OUT00P OUT01N OUT01P OUT02N OUT02P OUT03N OUT03P OUT04N OUT04P OUT05N
Ball # Ball Name
AF25 AE26 AC22 B26 AF24 AE24 AE23 AF23 AF22 AE22 AC21 AD21 AF21 AE21 AC20 AB19 AC19 AD20 AF20 AE20 AC17 AC18 AF19 AE19 AD18 AD19 AF18 AE18 AC16 AB16 AD16 AD17 AD15 AC15 AC14 AD14 AE17 AF17 AF16 AE16 AF15 AE15 AF14 AE14 IN20N IN20P IN21N IN21P IN22N IN22P IN23N IN23P IN24N IN24P IN25N IN25P IN26N IN26P IN27N IN27P IN28N IN28P IN29N IN29P IN30N IN30P IN31N IN31P IN32N IN32P IN33N IN33P IN34N IN34P IN35N IN35P IN36N IN36P IN37N IN37P IN38N IN38P IN39N IN39P IN40N IN40P IN41N IN41P
Ball # Ball Name
AE13 AD13 AB12 AC12 AE12 AD12 AD11 AC11 AF13 AF12 AF11 AE11 AE10 AF10 AE9 AF9 AC10 AD10 AC9 AD9 AC8 AD8 AC7 AD7 AF8 AE8 AE7 AF7 AE4 AF4 AB7 AC6 AE3 AF3 AE6 AD6 AF5 AF6 AE5 AD5 A3 B3 A4 B4 IN42N IN42P IN43N IN43P IN44N IN44P IN45N IN45P IN46N IN46P IN47N IN47P IN48N IN48P IN49N IN49P IN50N IN50P IN51N IN51P IN52N IN52P IN53N IN53P IN54N IN54P IN55N IN55P IN56N IN56P IN57N IN57P IN58N IN58P IN59N IN59P IN60N IN60P IN61N IN61P IN62N IN62P IN63N IN63P
Ball # Ball Name
A14 B14 A16 B16 B17 A17 A18 B18 D17 C17 D18 C18 B19 A19 D19 C19 E20 D20 A20 B20 B21 C20 D21 C21 B23 A23 B24 A24 A22 A21 C22 B22 E21 C26 C25 D26 D25 G22 F23 F24 G23 J23 H23 H24 OUT05P OUT06N OUT06P OUT07N OUT07P OUT08N OUT08P OUT09N OUT09P OUT10N OUT10P OUT11N OUT11P OUT12N OUT12P OUT13N OUT13P OUT14N OUT14P OUT15N OUT15P OUT16N OUT16P OUT17N OUT17P OUT18N OUT18P OUT19N OUT19P OUT20N OUT20P OUT21N OUT21P OUT22N OUT22P OUT23N OUT23P OUT24N OUT24P OUT25N OUT25P OUT26N OUT26P OUT27N
Ball #
G24 J24 K23 E25 E26 L22 L23 F25 F26 L24 K24 G25 G26 M24 M23 L26 L25 N24 N23 M26 M25 H25 H26 J25 J26 K26 K25 P24 N25 R23 R22 P25 N26 R24 T23 U22 U23 P26 R26 T26 T25 U26 U25 V24
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[Rev. 1.6] 2/20/01
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OCX160 Crosspoint Switch--Preliminary Data Sheet
Table 23 Ball Name
OUT27P OUT28N OUT28P OUT29N OUT29P OUT30N OUT30P OUT31N OUT31P OUT32N OUT32P OUT33N OUT33P OUT34N OUT34P OUT35N OUT35P OUT36N OUT36P OUT37N OUT37P OUT38N OUT38P OUT39N OUT39P OUT40N OUT40P OUT41N OUT41P OUT42N OUT42P OUT43N OUT43P OUT44N OUT44P OUT45N OUT45P OUT46N OUT46P OUT47N OUT47P OUT48N OUT48P OUT49N OUT49P OUT50N OUT50P
OCX160 Pinout By Ball Name (Continued) Ball # Ball Name
F2 E2 E1 G3 G4 F4 F3 C2 C1 D2 D1 C4 C5 AD22 AD23 AB6 AC5 AD4 AF2 AE1 AD1 AD2 AB4 AA5 E3 E4 F5 B1 D3 E6 D5 A25 AB21 AC25 AD26 AD25 D22 C23 D24 F22 E23 E24 E9 E10 E18 J5 J22 VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball # Ball Name
V25 T24 R25 V23 U24 W26 V26 W23 W22 W24 W25 AB26 AC26 Y25 Y26 AA25 AA26 AA24 AB25 Y23 Y24 AB23 AB24 AA22 AA23 AC3 AC2 AA4 Y5 AB3 AB2 Y4 W4 Y3 Y2 W3 V4 V1 V2 V3 U4 AC1 AB1 T5 T4 AA2 AA3 OUT51N OUT51P OUT52N OUT52P OUT53N OUT53P OUT54N OUT54P OUT55N OUT55P OUT56N OUT56P OUT57N OUT57P OUT58N OUT58P OUT59N OUT59P OUT60N OUT60P OUT61N OUT61P OUT62N OUT62P OUT63N OUT63P OUT64N OUT64P OUT65N OUT65P OUT66N OUT66P OUT67N OUT67P OUT68N OUT68P OUT69N OUT69P OUT70N OUT70P OUT71N OUT71P OUT72N OUT72P OUT73N OUT73P OUT74N
Ball # Ball Name
Y1 AA1 U3 U2 R4 R3 P3 P4 R2 R1 W1 W2 U1 T1 T2 T3 N3 P2 M4 M5 P1 N1 M3 L4 M2 L3 N2 M1 L1 L2 K1 K2 J1 J2 K5 K4 K3 J3 J4 H3 H4 H5 H1 H2 G1 G2 F1 OUT74P OUT75N OUT75P OUT76N OUT76P OUT77N OUT77P OUT78N OUT78P OUT79N OUT79P RCI2 RCI3 RCA0 RCA1 RCA2 RCA3 RCA4 RCA5 RCA6 RCB0 RCB1 RCB2 RCB3 RCB4 RCB5 RCB6 RC_CLK# RC_EN# RCI0 RCI1 RCO4 RCO0 RCO1 RCO2 RCO3 TCK TDI TDO TMS TRST# UPDATE# VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE
Ball # Ball Name
K22 U5 V5 V22 AB9 AB17 AB18 E7 E12 E16 E19 AB8 AB11 AB15 AB20 G5 H22 L5 M22 R5 T22 W5 Y22 A1 A2 A26 B2 B25 C3 C24 D4 D14 D23 E5 E13 E14 E17 E22 N4 N5 N22 P5 P22 P23 AB5 AB10 AB13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball #
AB14 AB22 AC4 AC13 AC23 AC24 AD3 AD24 AE2 AE25 AF1 AF26
I-Cube, Inc.
[Rev. 1.6] 2/20/01
37
OCX160 Crosspoint Switch--Preliminary Data Sheet
5.4 Package Dimensions
(BOTTOM VIEW)
(TOP VIEW)
(SIDE VIEW)
Figure 21 OCX160 Package--Bottom, Top and Side Views
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[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch--Preliminary Data Sheet
5.5 Package Thermal Characteristics
Table 24 Package PBGA NOTE:
1. Thermal performance values are based on simulation data.
Package Thermal Coefficients Pin Count 420
JC(C/W) JA(C/W) Still Air
1.7C/W
12C/W
I-Cube, Inc.
[Rev. 1.6] 2/20/01
39
OCX160 Crosspoint Switch--Preliminary Data Sheet 6. Power Consumption
There are two main factors to consider when calculating power consumption for the OCX160: * Power consumed by the chip * Power dissipated by the terminating resistors at the switch differential outputs The first component, chip power, consists of three integral elements (refer to Figure 22): 1. Input Power--This element is fixed (always ON) due to the DC current for differential outputs. 2. Core Power--This element is the same for LVDS or LVPECL outputs. Core power is a function of data rate (Mb/s) and the number of connection paths through the switch matrix. 3. Ouput Power--This element is a fixed amount for each differential output. The value is zero if the Output Enable (OE#) is disabled or set to OFF. The second component, termination power, is the power dissipated by the terminating resistors at the switch differential outputs. The value is zero if the Output Enable (OE#) is disabled or set to OFF. The following diagram shows the chip power elements (as described above), the formulas used for determining chip power, and the total power consumption as determined by the formula [Chip Power + Termination Power].
6.1 Power for LVDS I/O
Chip Power + Output Power Termination Power Termination Power
Input Power
(always ON)
Core Power
RS
Switch Matrix CLK
Output Buffer
RS
RDIV
4mW/Input
+
0.015mW/Mbs/Connection
+
4mW/Output
+
16mW/Output (Load)
Chip Power
Termination Power
Example: Worst Case = (4mW x 80) + (0.015 mW x 667 x 80) + (4mW x 80) 320mW
+
(16mW x 80) 1280mW 1280mW
+
800mW
+
=
320mW 1440mW
+ +
= 2.72 watts (total power consumption)
Figure 22 Power Consumption Diagram for the OCX160 using LVDS
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[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch--Preliminary Data Sheet
6.2 Power for LVPECL I/O
Chip Power + Output Power Termination Power Termination Power
Input Power
(always ON)
Core Power
RS
Switch Matrix CLK
Output Buffer
RS
RDIV
4mW/Input
+
0.015mW /Mbs/Connection
+
4mW/Output
+
28mW/Output (Load)
Chip Power
Termination Power
Example: Worst Case = (4mW x 80) + (0.015 mW x 667 x 80) + (4mW x 80) 320mW
+
(28mW x 80) 2240mW 2240mW
+
800mW
+
=
320mW 1440mW
+ +
= 3.68 watts (total power consumption)
Figure 23 Power Consumption Diagram for the OCX160 using LVPECL
I-Cube, Inc.
[Rev. 1.6] 2/20/01
41
OCX160 Crosspoint Switch--Preliminary Data Sheet 7. Component Availability and Ordering Information
OCXxxx - PPT
Family # I/O Ports Package Code
PB = Ball Grid Array
Temperature Range
Blank - Commercial (0C to 70C) I - Industrial (-40C to +85C)
8. Glossary
CLOCK: A single differential input used to gate data into registers in the Output Buffer. The input serves all outputs of the OCX. The neighbor input can also be used as a register clock. CROSSPOINT: A single cell controlled by two RAM bits. The RAM bits are connected in a master-slave configuration to provide an update for programming and changing program information all at once. CROSSPOINT ARRAY: An array of Crosspoint cells used to connect any input port to any output port. INPUT OR OUTPUT PATH: The signal flow from pin to array and array to pin. Each path has a register with selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on either side of the IO Buffer. NEXT NEIGHBOR: A physically adjacent port can be used as a clock source for an output configured in registered mode. These outputs are grouped in pairs such that the signal being switched through Output 0 can be used to clock the signal being switched through Output 1, or vice-versa. Any single clock or data input signal can be used to clock any other input signal provided they are switched to an appropriate output pair. PORT: A name followed by a number to identify a pin on the device. RAPIDCONFIGURE: A parallel programming method for the OCX devices. The RC mode uses 25 dedicated pins to program the Crosspoint Array and the IO Buffers. The 25 pins consist of an enable, a clock, four instruction bits, two seven-bit address fields, and a five-bit data field.
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[Rev. 1.6] 2/20/01
I-Cube, Inc.
OCX160 Crosspoint Switch--Preliminary Data Sheet
Revision History
Date/ 6/16/2000 9/25/00 Version No. Revision 1.0 Revision 1.1 Description Initial release of "Advanced" data sheet Additions include RCO output pin information, pinout drawing, pinout tables, package dimensions and illustration, duty-cycle diagram, thermal characteristics table, device reset options table, a section on configuring multiple devices, bitstream generation and downloading, JTAG information, and Power Consumption information/illustrations. Corrections to RC Programming table. Additions/corrections to multiple tables and timing diagrams. Updated RapidConfigure Read Cycle timing diagram so that RCO is relative to RC_CLK#; RCO was previously relative to RC_EN#. Replaced "+" on signal names to "P" and "-" to "N". Corrected RCO[4:0] pin locations. Changed product status definition from Advanced to Preliminary. Corrected Pinout drawing and Pinout tables to reflect that "P" and "N" are reversed on OUT40 to OUT79. Corrections to Table 22 "Pinout By Ball Sequence" to match Pinout drawing--changed ball name on T4 and T5 from OUT49N and OUT49P to OUT49P and OUT49N resepctively; ball # for IN07P corrected from AD20 to AE20. Corrections to Table 23 "Pinout By Ball Name" to match Pinout drawing--corrected IN07P ball # from AD20 to AE20; corrected OUT49P (T5) and OUT49N (T4) to be OUT49N (T5) and OUT49P (T4); corrected OUT50P (AA2) and OUT50N (AA3) to be OUT50N (AA2) and OUT50P (AA3). Changed the VIH, VIL, VOH, and VOL minimum and maximum values for LVPECL DC specifications in Table 20; added a note below table explaining the current values; changed Pass Transistor to proprietary high-performance buffering circuit.
10/20/00 11/16/00
Revision 1.2 Revision 1.3
11/21/00 12/14/00
Revision 1.4 Revision 1.5
1/20/2001
Revision 1.6
I-Cube, Inc.
[Rev. 1.6] 2/20/01
43
OCX160 Crosspoint Switch--Preliminary Data Sheet 9. Product Status Definition
Data Sheet Identification
Advanced
Product Status
Formative or In Design
Definition
This data sheet contains the design specifications for product development. Specification may change in any manner without notice. This data sheet contains the preliminary data, and supplementary data will be published at a later date. I-Cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. I-Cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications for a product that has been discontinued by I-Cube. The data sheet is provided for reference information only.
Preliminary
Preproduction Product
No Identification
Full Production
Obsolete
No longer in Production
I-Cube(R) is a registered trademark and RapidConnect, RapidConfigure, ActiveArray, ImpliedDisconnect, IQ, IQX, MSX, MSXPro, OCX, OCXPro, and PSX are trademarks of I-Cube, Inc. All other trademarks or registered trademarks are the property of their respective holders. I-Cube, Inc., does not assume any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights of others. The information contained in this document is believed to be current and accurate as of the publication date. I-Cube reserves the right to make changes, at any time, in order to improve reliability, function, performance or design in order to supply the best product possible. I-Cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. This product is protected under the U.S. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814, 5559971, 5625780, 5710550, 5717871, 5734334, 5781717, 5790048. Additional patents pending. OCX160 Crosspoint Switch Data Sheet-- Rev 1.6, February 2001 Copyright (c) 1992-2001 I-Cube, Inc. All rights reserved. Unpublished--rights reserved under the copyright laws of the United States. Use of copyright notices is precautionary and does not imply publication or disclosure.
I-Cube(R), Inc.
2605 S. Winchester Blvd. Campbell, CA 95008 USA Phone: Fax: Email: Internet: +(408) 341-1888 +(408) 341-1899 marketing@icube.com http://www.icube.com OCX160 Crosspoint Switch Data Sheet Revision 1.6, February 2001 Document#: MKT-OCX-DS_Rev+1+dot+6
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[Rev. 1.6] 2/20/01
I-Cube, Inc.

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